1. Field of the Invention
This invention generally relates to transistor circuit design and, more particularly, to a transistor circuit design for minimizing threshold offset voltage and bias current errors in a comparator circuit.
2. Description of the Related Art
FIG. 1 is a schematic block diagram of a self-referencing comparator (prior art). A comparator is an important component of a digital signal receiver decision circuit, such as a serial communications optical network, where the input data signal is compared to a preset differential amplifier threshold. In some cases, in order to dynamically track the common mode or dc value of the input signal, an integrator is used for averaging the input signal, to create the comparator threshold. The integrator normally consists of a RC network, as shown in FIG. 1.
One shortcoming of this arrangement is the occurrence of a threshold offset voltage, due to the dc bias current at the comparator input. That is, the flow of current xcex94i across the resistor creates a voltage drop xcex94v, and the dc voltage at the positive terminal of the comparator is offset xcex94v from the dc voltage at the negative terminal. This offset voltage can affect the sensitivity of the comparator and may result in decision circuit bit errors. When this offset voltage is critical, designers can implement additional circuitry to mitigate to effect of the threshold offset voltage. However, while some techniques are able to mitigate for a first order magnitude of the effect. Additional second and third order offset voltage effects may still account for significant decision circuit errors, especially in advanced silicon germanium (SiGe) process devices.
FIG. 2 is a schematic diagram of a differential amplifier circuit, such as may be used in the comparator of FIG. 1 (prior art). The differential amplifier may receive ac signals on the xe2x80x9cdata outxe2x80x9d line (see FIG. 1). In additional, the differential amplifier receives a dc bias current supplied by the dc bias circuitry. The dc bias circuitry typically uses current mirrors to simulate the current flow through the differential amplifier. However, differences between the simulated current flow and the actual current flow through the differential amplifier may result in incorrect dc biasing. Improper dc biasing can also create additional threshold offset voltages that result in decision circuit errors.
It would be advantageous if the threshold offset voltage between the inputs of a comparator could be reduced.
It would be advantageous if differential amplifier dc biasing errors could be reduced.
The present invention discloses circuitry to reduce dc threshold offset voltage and dc bias current errors in a comparator. In one aspect of the invention, an operational amplifier senses the threshold voltage difference and provides the actual threshold voltage the comparator input, bypassing the offset current of the comparator input stage. In another aspect, the dc bias circuitry associated with a comparator input differential amplifier stage is modified to include a load that more realistically models the actual load of the differential amplifier, so that the current flow through the current mirror more closely resembles the current flow through the differential amplifier.
Accordingly, a system is provided for reducing the threshold bias offset voltage in a comparator, by canceling and bypassing the bias offset current errors. The system comprises a comparator including an emitter-coupled transistor pair including a first and second transistor that operates as the input differential amplifier stage. A first current mirror is connected to bias the first transistor. The system further comprises a third transistor, equivalent to the first transistor. A second current mirror, in parallel with the first current mirror, biases the third transistor.
The first current mirror includes a fourth transistor having an emitter connected to the base of the first transistor and uses a first diode interposed between a first voltage (Vcc) and the base of the fourth transistor. The second current mirror includes a fifth transistor having an emitter connected to the base of the third transistor. The first diode is interposed between the first voltage and the base of the fifth transistor.
A first current source is interposed between the emitters of the first and second transistors, and a second voltage (Vee), lower in potential than the first voltage. A second current source is interposed between the emitter of the third transistor and the second voltage. A third current source is interposed between the emitter of the fourth transistor and the second voltage, and a fourth current source is interposed between the emitter of the fifth transistor and the second voltage.
The above-described bias offset current cancellation circuit cancels the base current of the comparator input stage emitter follower (fourth transistor), and the loading effects of the fourth transistor""s driving stage.
The threshold-setting network of the comparator includes two integrators and a unit gain amplifier, formed from an operational amplifier. The first integrator has an input to accept a single-ended input signal, connected to the positive input of the comparator, and the output connected to the negative input of the comparator. A second integrator has an input connected to the input of the first integrator. The operational amplifier has a positive input operatively connected to the output of the second integrator, and an output connected to the operational amplifier negative input, the output of the first integrator, and the negative input of the comparator. The first integrator has a frequency response equal to the frequency response of the second integrator.
Additional details of the above-described differential amplifier biasing circuit and system for the cancellation of threshold offset voltage in a comparator are provided below.